(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming short channel MOSFET transistors with source/drain extensions in the fabrication of integrated circuits.
(2) Description of the Prior Art
In photolithography, various mask patterns distinguish between the parts that are to be etched and the parts that should remain. However, due to diffraction effects, the boundary regions of the mask pattern may not be well defined, especially when the line width of the mask patterns approaches that of the light wavelength. Therefore, as the gate width of semiconductor devices continues to be reduced, it is increasingly difficult to fabricate devices with dimensions of less than 0.1 micron by using conventional lithography methods. It is desired to find a method of forming short channel MOS transistors that will solve this problem.
A number of workers in the art have proposed trench type MOSFET fabrication methods. U.S. Pat. No. 6,133,106 to Evans et al discloses source/drain regions and gate of the same height where the gate is formed by a dummy gate replacement method. U.S. Pat. No. 6,100,146 to Gardner et al shows a trench etch process. U.S. Pat. No. 6,258,679 to Burns et al shows a damascene gate process. U.S. Pat. No. 6,214,670 to Shih et al teaches a short channel trench process to form a metal gate.
A principal object of the present invention is to provide an effective and very manufacturable method of forming a short channel MOSFET device.
A further object of the invention is to provide a method of forming short channel MOS transistors using existing lithographic technologies and mask sets.
Yet another object is to provide a method of forming short channel MOS transistors having an increased gate width.
A further object is to provide a method of forming short channel MOS transistors having an increased gate width using existing lithographic technologies and mask sets wherein the gate resistance is reduced.
A still further object is to provide a method of forming short channel MOS transistors having an increased gate width using existing lithographic technologies and mask sets wherein parasitic capacitance is reduced.
In accordance with the objects of this invention a novel method for forming short channel MOS transistors is achieved. A hard mask stack is formed over a substrate. A first opening is formed through a top portion of the hard mask stack. Oxide spacers are formed on sidewalls of the first opening thereby forming a second opening smaller than the first opening. The second opening is filled with a polysilicon layer. Thereafter, the oxide spacers are removed. First ions are implanted into the substrate underlying the removed oxide spacers to form source/drain extensions. Then, the polysilicon layer is removed wherein the first opening remains and wherein the substrate is exposed in a channel region. A gate dielectric layer is formed over the channel region. The first opening is filled with a gate electrode material that is polished back to form a gate electrode. The hard mask stack is removed using the gate electrode as a mask. Second ions are implanted to form source/drain regions within the substrate adjacent to the gate electrode to complete formation of a short channel MOS transistor in the fabrication of an integrated circuit device.